New computing system to enable deep space missions

A new radiation-hardened, multi-processor, Arm-based spacecraft processor is being developed at Michigan in a project led by Boeing and funded by NASA.

Chiplet-powered spacecraft Enlarge
The radiation-hardened Chiplet will dramatically boost the processing power of future spacecraft. Image courtesy of NASA.

In space, radiation can disrupt or even destroy electronic circuits, which makes radiation-hardened, multi-processor, high-reliability computing systems essential for deep space exploration. In a project led by Boeing and working with Prof. Ron Dreslinski at the University of Michigan that is funded by NASA, a new Arm-based spacecraft processor technology is being developed to meet this challenge, which is known as the HPSC (High-Performance Spaceflight Computing) Chiplet.

HPSC Chiplet-powered systems will replace decades-old processor technology with a modern power-efficient Arm system-on-chip (SoC) design, and will provide orders of magnitude more computer processing power than is found in spacecraft of today. This will allow for enhanced capabilities such as onboard autonomy, astronaut assistance, and high bandwidth sensor data processing, and could provide a path forward for increasingly intelligent spacecraft.
Although the systems that run today’s spacecraft are radiation-hardened, they do not provide the performance characteristics of modern processors. The HPSC Chiplet’s radiation-hardened design will provide reliability comparable to that of current systems, but in a smaller, lighter package that drastically improves compute capabilities and energy-efficiency.

Who’s working on the HPSC project

Development of the HPSC Chiplet is funded by the Game Changing Development program within NASA’s Space Technology Mission Directorate and the Science Mission Directorate in Washington. The overall HPSC project is managed by the Jet Propulsion Laboratory, with the Chiplet acquisition managed by the Goddard Space Flight Center. Additionally, the Air Force Research Lab, Space Vehicles Directorate, has closely collaborated on this project to ensure that the Chiplet will be relevant to their mission requirements.

HPSC Chiplet development is being led by Boeing. For the research and development side of the project, Boeing turned to the University of Michigan and Arm. The two entities have enjoyed a unique, long-standing, and productive partnership for over a decade – including the Michigan-Arm Research Center (MARC).

Prof. Dreslinski is working as the chief architect for the HPSC Chiplet design, leveraging the extensive background in Arm IP that he has acquired through the MARC.

What will the design look like?

The SoC system will incorporate a high performance subsystem to handle high throughput computation, a real-time processing subsystem for timing critical applications, and a host of interconnects that can be used to create multi-chiplet systems or to interface with sensors and actuators.
Arm technology provides a robust real-time processor (Cortex-R class processor) that can be utilized for hard real-time computation, while their preeminence in low-power designs will facilitate energy-efficient but highly capable scientific computation engines (Cortex-A class processors). The Arm quality-of-service capabilities (QoS/QVN) provide a mechanism to manage demands for on-chip resources, while their TrustZone technology provides isolation of sub-systems and security for Air Force deployments.

About the U-M/ARM relationship

The Michigan-Arm Research Center (MARC) was established in 2004 and is led by Bredt Family Professor of Computer Science and Engineering Trevor Mudge. It is a collaborative effort that has allowed U-M to build test chips using commercial IP in advanced technology nodes to validate research.
As a part of MARC, U-M has filed over 100 patents that have been assigned to Arm, and has fabricated and tested over 100 designs over the last 10 years of research. These include groundbreaking work in variation tolerant design using automatic timing error detection and correction, ultra-low power sub-threshold designs, high performance crossbar designs, and the first near-threshold designs, including a 64-core Arm processor design using 3D through-silicon-via (TSV) technology.